When BUFGCE_DIV buffers have BUFGCE_DIVIDE set to a value greater than
1, they must share common control signals to avoid phase ambiguity caused by differences
in the internal state of each buffer. Without common CE and CLR signals, the buffers can
reset on different clock cycles, creating an unknown clock relationship between their
outputs. This situation can lead to hardware failure. TIMING-49 is not limited to
parallel BUFGCE_DIV buffers driven by the same clock modifying block (CMB) and applies
to all synchronous topologies that must be safely timed.
Figure 1. Correct Implementation of BUFGCE_DIV Buffers
