For UltraScale™ devices, Vivado automatically derives clocks on the output of a GT based on the GT settings and the characteristics of the incoming master clock. For 7 series devices, Vivado does not automatically derive the GT clocks; it is your responsibility to create the appropriate primary clocks on the GT's output pins. The DRC warning is reporting that the user-defined clock does not match the expected auto-derived clock that Vivado would automatically create. This could lead to hardware failures as the timing constraints for the design do not match what happens on the device.