In 7 series and UltraScale
devices, a phase-shifted output of an MMCM or PLL is modeled by default as a change in
the clock waveform (PHASESHIFT_MODE=WAVEFORM). In this mode, the edges
of the clock waveform shift to reflect the pin phase shift.
In UltraScale+ devices, the pin phase shift
is modeled by default as a latency propagation delay through the clock modifying block
(PHASESHIFT_MODE=LATENCY), without changing the clock waveform.
In waveform mode, multicycle constraints might be required to adjust the timing path requirement for the phase shift between the source and destination clock waveforms. In latency mode, these constraints are typically unnecessary.
For more information on phase shift modes, refer to MMCM/PLL Phase Shift Modes.