Vivado automatically derives clocks on the output of a clock modifying block (CMB) based on the CMB settings and the characteristics of the incoming master clock. If you define a generated clock on the output of the CMB, Vivado does not auto-derive a generated clock on the same definition point (net or pin).
The DRC warning is reporting that the user-defined generated clock does not match the expected auto-derived clock that Vivado would automatically create. This could lead to hardware failures because the timing constraints for the design do not match the behavior in hardware.