For UltraScale devices, Vivado automatically derives clocks on the output of a GT based on the GT settings and the characteristics of the incoming master clock. For 7 series devices, Vivado does not automatically derive GT clocks, so a primary clock must be created on the GT output pins. This DRC warning indicates that the defined clock does not match the expected auto-derived clock that Vivado would generate. This mismatch can result in hardware failures because the timing constraints do not reflect actual device behavior.