In 7 series and
UltraScale, a phase-shifted output of an MMCM or
PLL is modeled by default as a change in the clock waveform (PHASESHIFT_MODE=WAVEFORM). This signifies that the edges of the clock
waveform are shifted to account for the pin phase shift.
In UltraScale+,
the pin phase shift is modeled by default as a latency propagation delay through the
clock modifying block (PHASESHIFT_MODE=LATENCY) with no change in the
clock waveform.
In WAVEFORM mode, multicycle constraints might be needed to
adjust the timing path requirement due to the phase shift introduced between the source
and destination clock waveforms. In LATENCY mode, these multicycle path
constraints are no longer required.
For more information on phase shift modes, see MMCM/PLL Phase Shift Modes.