This check applies to Versal adaptive SoC only.
When the MMCM, XPLL, or DPLL is configured with digital deskew, the pin phase shift can only be modeled as a latency delay through the CMB and not as a change in the clock waveform. If the element is set to PHASESHIFT_MODE=WAVEFORM, the timer cannot honor waveform modeling and instead enforces latency modeling. This does not affect sign-off timing accuracy because the latency model is applied automatically.