IO timing is in reference to a timing path that includes an external device. The input and output delays specify the paths delay of the ports relative to a clock edge at the interface of the design. It is highly recommended to add input/output delay constraints to ensure that the FPGA interface can meet the timing of the external devices.
Note: A TIMING-18 violation is reported for any missing
clock edge. If a clock is inverted during the clock network propagation (including on
the primitive clock pin) and an input or output delay is expected but missing for the
falling clock edge, a TIMING-18 violation is generated although the missing clock edge
is not specified inside the message.