A LUT on a clock path can cause excess skew because the clock must be routed through general routing resources in the fabric rather than dedicated clock routing. In addition to increased skew, these paths are more susceptible to process, voltage, and temperature (PVT) variations.
This situation can be created during synthesis in cases such as clock gating or
inversion. For example, an inversion LUT1 cell might be absorbed into the downstream
SLICE after opt_design.