This check applies to Versal adaptive SoC only.
In these devices, it is safe to time between the DPLL input clock and one of its
output clocks only when the phase detector (CLKOUTx_PHASE_CTRL=01) is used and the CLKIN_DESKEW pin is connected to
the CLKIN pin. In all other cases, the phase relationship between the master clock and
the auto-derived clocks is unknown. The clock domain crossing between them must be
considered asynchronous, and any path in the crossing must include synchronization logic
in the destination clock domain.