Synchronous clocking topologies with BUFGCE_DIV buffers that have BUFGCE_DIVIDE>1 must have common control signals to prevent a phase ambiguity that might occur from the internal state of the BUFGCE_DIV. Such a situation could lead to the clock buffer being reset during different clock cycles and the outputs of the BUFGCE_DIV to have an unknown clock relationship. The design could fail in hardware. The following diagram shows the correct implementation of the circuit:
Note: TIMING-49 is not restricted to parallel BUFGCE_DIV driven by the same CMB. The check covers all synchronous topology that are safely timed.
Figure 1. Correct Implementation of BUFGCE_DIV Buffers
