Description - 2025.1 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-05-29
Version
2025.1 English

There should not be a false_path, set_clock_group -asynchronous, or set_max_delay -datapath_only constraint on a synchronous clock domain crossing. With such constraints, the paths will not be properly timed, the sign-off timing will be inaccurate, and the design could fail in hardware.