The dataflow netlist is a subset of your original design netlist. When you generate the dataflow netlist, Vivado trims out the following:
- Scalar nets
- Bus nets below the
-min_bus_widththreshold (default:16) - Registers
- LUTs that do not significantly influence the datapath
The dataflow netlist includes the following:
- Bus nets equal to or above the
-min_bus_widththreshold - Significant cells that impact placement include the following items:
- BlockRAMs
- UltraRAMs
- LUTRAMs
- DSP slices
- Hard IP
- Gigabit transceivers
- NoC
- Hierarchical cells
- Clock nets