Dataflow Netlist Generation - 2024.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2024-06-05
Version
2024.1 English

The dataflow netlist is a subset of the original design netlist. When the dataflow netlist is generated, the following items are trimmed out:

  • Scaler nets
  • Bus nets below the -min_bus_width threshold (Default:16)
  • Registers
  • LUTs that are not considered significant datapath influences

The following items make up the dataflow netlist:

  • Bus nets equal to or above -min_bus_width threshold
  • Significant cells that impact placement. These include:
    • BlockRAMs
    • UltraRAMs
    • LUTRAMs
    • DSP Slices
    • Hard IP
    • Gigabit Transceivers
    • NoC
  • Hierarchical Cells
  • Clock nets