Clock Pair Classification - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The Clock Pair Classification column explains why the tool considers two clocks synchronous or asynchronous. The tool stops checking as soon as it detects one of the conditions below, listed in order of priority:

Ignored
A clock group, false path, or max delay datapath-only constraint covers the entire clock pair.
Note: When a clock pair is covered by a max delay datapath only, the Inter-Clock Constraints are reported as Max Delay Datapath Only during setup analysis and as Auto Generated False Path during hold analysis (-delay_type min).
Virtual Clock
One or both clocks are virtual, so common primary clock or node checks do not apply
No Common Clock
The clocks do not share a common primary clock
No Common Period
The periods are not expandable
Partial Common Node
The two clocks appear synchronous, but a subset of the crossing paths does not have a common node and cannot be safely timed
No Common Node
The two clocks appear synchronous, but the crossing paths do not have a common node
No Common Phase
The clocks lack a known phase relationship
Clean
None of the above conditions apply.