Check Timing Section - 2025.2 English - UG906

The Check Timing section of the Timing Summary Report lists issues related to missing or incomplete timing constraints. For complete timing signoff, you must constrain all path endpoints.

For more information on defining constraints, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).

To generate Check Timing as a standalone report, do one of the following:

• In the Vivado IDE, select the Reports > Timing > Check Timing menu command.
• Run the check_timing Tcl command.

When running from the Tcl Console, you can use the -cells option to scope the report to specific hierarchical cells. This option is not available in the GUI.

Common checks reported in this section (as shown in the previous figure) include the following:

pulse_width_clock

Reports clock pins that have only a pulse width check, with no setup, hold, recovery, removal, or clk-to-Q check.

no_input_delay

Reports non-clock input ports that are missing input delay constraints.

no_clock

Reports clock pins not reached by a defined timing clock. This also includes constant-driven clock pins.

constant_clock

Flags clock signals that are connected to a constant (such as GND, VSS, or static data).

unconstrained_internal_endpoints

Reports path endpoints (excluding output ports) with no timing requirement. These often result from missing clock definitions and can be related to no_clock.

no_output_delay

Reports non-clock output ports without at least one output delay constraint.

multiple_clock

Reports clock pins reached by more than one timing clock. This usually indicates a multiplexer in the clock tree. Only one clock can drive a clock tree at a time. Review the design if multiple clocks are unexpectedly present.

generated_clocks

Reports generated clocks with a master source that is not in the same clock tree. This can happen when a timing arc is disabled between the master clock and the generated clock's source. If you use the -edges option, the logical unateness (inverting/non-inverting) must match the edge relationship.

loops

Reports combinational loops found in the design. Vivado breaks these loops automatically for timing analysis.

partial_input_delay

Reports input ports that have only a min or max input delay constraint, but not both. These paths are excluded from either setup or hold analysis.

partial_output_delay

Reports output ports that have only a min or max output delay constraint. These are also excluded from complete timing analysis.

latch_loops

Reports loops that pass through latches. These are not included in regular combinational loop checks and can affect latch time borrowing calculations.

Use this section to identify and resolve constraint issues that could compromise the accuracy of your timing analysis.