Review properties that might block optimization:
- Combined LUT Pairs can restrict placement and increase congestion. If this causes
issues, disable LUT combining in synthesis using the
-no_lcoption. - MARK_DEBUG and DONT_TOUCH identify objects that cannot be optimized. By default, setting MARK_DEBUG also sets DONT_TOUCH.
If optimization is blocked:
- Set DONT_TOUCH to FALSE where appropriate.
- Avoid using DONT_TOUCH unless needed for logic preservation.
- If a net crosses into a hierarchical cell marked with DONT_TOUCH, only the external portion can be optimized.
If the path has fixed placement or routing:
- Fixed Loc and Fixed Route show constraints that might restrict timing optimization.
- Fixed cell locations can help stabilize timing but might prevent recovery after design changes.
- Fixed routes prevent delay optimization. Use them only when necessary, and ensure they don't negatively affect connected paths.
- If you modify physical constraints like Pblocks, update fixed placement and routing constraints as needed.