Logic characteristics describe the basic path structure:
- Start Point Pin Primitive and End Point Pin Primitive show the types of the starting and ending cells. Confirm these are expected for your design.
- Start Point Pin and End Point Pin provide the exact pin locations.
- Logic Levels and Logical Path summarize path depth and primitive usage.
- Routes indicate the number of routable nets in the path.
Check for control signals like CLR, PRE, RST, and CE that often appear on high-fanout nets. Paths with DSPs or block RAMs tend to have tighter timing budgets due to longer Clock-to-Q delays.
If you see mostly LUTs in the path, investigate:
- Why smaller LUTs are used instead of larger LUT6s.
- Whether constraints like KEEP, DONT_TOUCH, or MARK_DEBUG are limiting synthesis optimization.
- Whether changing synthesis options or using
opt_design -remapcan reduce logic depth.
Look at the presence of DSPs or RAMs. Timing is harder to meet when these cells are not registered and are followed by deep logic.