Timing characteristics include Path Type, Requirement, Slack, and Timing Exception. These
fields help you understand the type of analysis (SETUP or HOLD), whether the timing is
met, and if any exceptions apply (such as multicycle or
max_delay).
When debugging missing or incorrect timing constraints, check the path requirement first:
- Review setup paths with requirements under 4 ns, especially for clock domain crossing paths.
- Investigate paths with setup requirements under 2 ns. These are difficult to meet and usually indicate a problem.
- For paths with small setup requirements, look for missing timing exceptions or incorrect clock relationships.
- Check for positive hold requirements. These are uncommon and usually signal that multicycle hold constraints are missing or applied only to setup.
- Examine source and destination clocks to confirm expected edge alignment.
For the datapath, review the Path Delay, Logic Delay, and Net Delay values:
- If Logic Delay accounts for more than 50% of the total path delay, examine logic depth and cell types. You might need to change the RTL or synthesis settings.
- If Net Delay dominates a path with a reasonable requirement, look at physical and property characteristics. Check for high fanout nets or hold fix detours.
- In 7 series devices, LUT delay is included in net delay. In UltraScale devices, it appears under logic delay. Expect higher Net Delay to Logic Delay ratios in 7 series architectures.