The following figure shows a clock enable controlled CDC example. In this structure, the
clock enable signal is synchronized in the clk_b domain before it
controls the crossing flip-flops.
Figure 1. CE-Controlled CDC Example
The CDC engine checks only that the signal connected to FF3/CE is
launched by clk_b. It does not place restrictions on how the clock
enable signal is synchronized or on the circuitry driving the CE pin,
as long as that path is independently reported as a safe CDC.
You are responsible for constraining the latency from the clk_a domain
to FF3. To do this, apply a set_max_delay
-datapath_only constraint.