Bus Skew Report Summary Section - 2025.2 English - UG906

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2025-12-10
Version
2025.2 English

The Bus Skew Report Summary lists all set_bus_skew constraints defined in the design. For each constraint, the report includes the following:

Id
A unique identifier used throughout the report to help you locate and track each constraint
From
The pattern you specified with the set_bus_skew -from option
To
The pattern you specified with the set_bus_skew -to option
Corner
The analysis corner (Slow or Fast) where the report found the worst bus skew
Requirement
The skew limit you defined for the constraint
Actual
The worst bus skew value found across all paths covered by the constraint
Slack
The difference between the actual skew and the requirement

In the following example, the design has one bus skew constraint with a 1 ns requirement and the worst skew observed is 1.107 ns, the report flags it as a violation.
Note: A bus skew violation (WBSS) means the timing difference between bits of an asynchronous bus exceeds the expected limit. This can cause incorrect data capture in the destination clock domain, where different bits could reflect a state sent by the source clock domain at different clock cycles. If any WBSS violations remain after routing, try using a different placement or routing directive. To maintain hardware stability, make sure no bus skew violations remain in the design.