Asynchronous Reset Synchronizer - 2025.2 English - UG906

The asynchronous reset synchronizer ensures that the reset signal is safely deasserted in the destination clock domain. The following figures show two types of synchronization:

• Clear-based synchronization
• Preset-based synchronization

In each case, the FF1 cell connects to the synchronized clear or preset signal, and the deassertion is safely timed against clk_a.

Important considerations:

• Do not mix flip-flops with CLEAR and PRESET in the same asynchronous reset synchronizer.
• Avoid multiple synchronizations of the same reset signal inside the destination clock domain. Multiple synchronizations can cause parts of the destination logic to exit reset at different times, potentially placing the system in an unknown state. This issue is reported as a critical CDC-11 violation (fanout from launch flop to destination clock).

However, certain scenarios allow safe multiple synchronizations of the reset signal:

• The FIFO Generator IP safely handles reset synchronization by entering reset asynchronously and exiting reset synchronously. Although the block RAM receives a synchronous reset, the reset input to the FIFO Generator remains asynchronous. If your design uses the wr_rst_busy signal to control data flow, then reset release timing is safe across the logic.
• The AXI interface uses five FIFO Generator IPs to synchronize reset signals independently within each destination clock domain. This architecture safely manages multiple reset synchronizations by design.

In such cases using the FIFO Generator IP, you can ignore CDC-11 violations reported for reset fanout.