Note: This section refers only to the place_design
command for Versal families. For other families, refer to place_design Command (7 Series and UltraScale).
The place_design command runs placement on the
design. Like the other implementation commands, place_design is re-entrant in nature. For a partially placed design,
the placer uses the existing placement as the starting point instead of starting
from scratch.
place_design Syntax
place_design [-directive <arg>] [-subdirective <args>] [-no_timing_driven]
[-timing_summary] [-unplace] [-no_psip] [-no_noc_opt]
[-clock_vtree_type <arg>] [-net_delay_weight <arg>]
[-quiet] [-verbose]
| PSIP Optimization | Applicable on which objects |
|---|---|
| Critical cell | Nets |
| Fanout | Nets |
| Very high fanout | Nets |
| Equivalent Driver Rewire | Nets |
| DSP Register | Cells |
| Block RAM Register | Cells |
| URAM Register | Cells |
| Shift Register | Cells |
| Logic Retiming | Cells |
| Per SLR Replication | Nets |
| Dynamic/Static Region Interface Net replication | Nets |
| Shift Register to Pipeline | Cells |
| Auto Pipeline Insertion | Nets |
| Control Set optimization | Cells |