The phys_opt_design command runs physical optimization on the
design. It can be run in post-place mode after placement and in post-route mode
after the design is fully-routed.
phys_opt_design Syntax
phys_opt_design [-fanout_opt] [-placement_opt] [-routing_opt]
[-slr_crossing_opt] [-insert_negative_edge_ffs]
[-restruct_opt] [-interconnect_retime] [-lut_opt] [-casc_opt]
[-cell_group_opt] [-critical_cell_opt] [-dsp_register_opt]
[-bram_register_opt] [-uram_register_opt] [-bram_enable_opt]
[-shift_register_opt] [-hold_fix] [-aggressive_hold_fix]
[-retime] [-force_replication_on_nets <args>]
[-directive <arg>] [-critical_pin_opt] [-clock_opt]
[-path_groups <args>] [-tns_cleanup] [-sll_reg_hold_fix]
[-quiet] [-verbose]
-tns_cleanup option can only be run with the -slr_crossing_opt option.phys_opt_design Example Script
open_checkpoint top_placed.dcp
# Run post-place phys_opt_design and save results
phys_opt_design
write_checkpoint -force $outputDir/top_placed_phys_opt.dcp report_timing_summary -file $outputDir/top_placed_phys_opt_timing.rpt
# Route the design and save results
route_design
write_checkpoint -force $outputDir/top_routed.dcp
report_timing_summary -file $outputDir/top_routed_timing.rpt
# Run post-route phys_opt_design and save results
phys_opt_design
write_checkpoint -force $outputDir/top_routed_phys_opt.dcp report_timing_summary -file $outputDir/top_routed_phys_opt_timing.rpt
The phys_opt_design example script runs both post-place and
post-route physical optimization. First, the placed design is loaded from a
checkpoint, followed by post-place phys_opt_design. The checkpoint
and timing results are saved. Next the design is routed, with progress saved
afterwards. That is followed by post-route phys_opt_design and
saving the results. Note that the same command phys_opt_design is
used for both post-place and post-route physical optimization. No explicit options
are used to specify the mode.
The phys_opt_design -clock_opt command additionally focuses on taking advantage of
useful clock skew for COE blocks, targeting BRAM, URAM, and DSP blocks. The process
is executed in the pre-route phys_opt_design stage as an extension of the
clock_opt switch, aimed at optimizing COE paths.
- Clock Skew Application
- phys_opt_design takes advantage of useful skew using CLK_MODs in IRI_QUADs driving the macro clock pins to improve negative setup slack
Phase Based Optimization
- During phase-based clock optimization iterations, specific block types like URAM, BRAM, and DSP are optimized to take advantage of useful clock skew. PCIe blocks are not currently optimized during the phase-based execution but are optimized during path-based execution of phy_opt_design.
- Phase-based optimization involves dividing the optimization process into distinct phases, each targeting different aspects or areas of the design.
Usage
phys_opt_design -clock_opt
Path-Based Clock Optimization
Timing path based optimizations take a failing timing path and try multiple optimizations to improve the performance of the path. This approach is particularly useful for improving the timing of critical paths that might be limiting the overall performance of the design. It allows for incremental updates to timing after each optimization, which helps in assessing the impact of changes on the design's performance.
Usage
phys_opt_design
In some designs, there might not be enough output slack available to effectively borrow during this optimization process. This can limit the extent of improvements achievable for PCIe and other COE blocks.