Physical Synthesis Phase - Physical Synthesis Phase - 2026.1 English - UG904

During physical synthesis in the placer (PSIP), the placer can perform various physical optimizations that will optimize the netlist for later placement phases based on the initial placement of the design after the floorplanning stage. For example, for fanout based replication the replicated driver can be co-located with its loads because the initial placement is known. This alleviates congestion that can be introduced when replication is done without knowledge of placement prior to place_design. Optimizations are considered based on internal parameters and for timing based optimizations the timing is evaluated and the optimization is committed if timing is improved. The following optimizations are available as shown in the following figure.

SLR Replication

High fanout nets that connect a single driver to multiple loads, can present timing challenges when these loads are distributed across different SLRs. SLR replication replicates the driver of high fanout nets which has critical loads in other SLRs. Drivers are selected based on timing estimates after Floorplanning phase of placer. In this optimization all soft and hard Pblock constraints are honored.

Control Set Optimization

Performs control set reduction with more accurate placement location information. With meaningful initial placement result, the flops are distributed among the placement area, and flop minimal resource usage for the exactly flops in a small region is calculated. For the hotspot regions, it finds an optimal solution to reduce the resource usage. Therefore, reduce the legalization effort to push cells further in downstream and leave more room for other optimizations. This phase is activated during placer's Explore directive only.

Auto Pipeline Insertion

Auto Pipeline Insertion is a non-timing driven optimization that inserts pipeline registers on user marked nets. This feature is used to address timing closure challenges on specific buses and interfaces. Once pipeline stages have been inserted, the placer adjusts pipeline locations to improve clock speed. See Auto-Pipelining for more information.

Retiming

Retiming is a default optimization during PSIP. It automatically moves registers across combinational logic to balance pipeline stages and improve timing. In addition to automatic retiming, property-based retiming provides user-controlled retiming through setting a property on a register or LUT.

Retiming can be a useful optimization in the following circumstances:

• Critical paths have high logic levels (many LUTs in series).
• The critical path is through combinational logic.
• Adjacent pipeline stages are unbalanced, meaning that one stage has deep logic with negative slack while the neighboring stage has shallow logic with positive slack.
• Datapath delay dominates the timing violation.
• There are large WNS violations early in the flow.

Property-Based Retiming

Property-based retiming provides user-controlled retiming through setting a property on a register or LUT. This optimization is ideal for critical paths with sufficient margin on timing startpoints or endpoints. Two properties control retiming in PSIP, as shown in the following table.

Table 1. Retiming in PSIP Properties

Property	Value	Description
PSIP_RETIMING_FORWARD	TRUE	Performs forward retiming.
PSIP_RETIMING_BACKWARD	TRUE	Performs backward retiming.

The properties can be applied to a register or LUT as follows:

• When PSIP_RETIMING_FORWARD with value TRUE is applied to a register, PSIP forward-retimes over all LUT loads driven by the Q pin of the register.
• When PSIP_RETIMING_FORWARD with value TRUE is applied to a LUT primitive, the register driving the LUT is moved to the output of the LUT.
• When PSIP_RETIMING_BACKWARD with value TRUE is applied to a register, PSIP backward-retimes over the LUT driving the D pin of the register. the backward retiming property on the register does not trigger backward retiming over control set pin driver LUTs.
• When PSIP_RETIMING_BACKWARD with value TRUE is applied to a LUT primitive, the register driven by the LUT is moved to LUT inputs.

Multi-level retiming is supported by applying the property to all LUT primitives along the path. All retimed cells have the PHYS_OPT_MODIFIED property set to RETIMING.

Retiming does not work in the following circumstances:

• Moving logic across macros, such as block RAM, UltraRAM, and DSPs
• Registers packed in I/O sites
• Paths with different startpoint/endpoint clocks
• Paths with timing exceptions
• Paths with properties that prevent optimization, such as DONT_TOUCH and ASYNC_REG

Very High-Fanout Optimization

Very High-Fanout Optimization replicates registers driving high-fanout nets (fanout > 1000, slack < 2.0 ns).

Critical Cell Optimization

Critical-Cell Optimization replicates cells in failing paths. If the loads on a specific cell are placed far apart, the cell might be replicated with new drivers placed closer to load clusters. This optimizations often applies to nets driving large block RAM or URAM arrays or large number of DSPs as the sites for these blocks are spread over a wider area of the device. High fanout is not a requirement for this optimization to occur (slack < 0.5 ns).

Fanout Optimization

Nets with a MAX_FANOUT property value that is less than the actual fanout of the net are considered for fanout optimization. You can force the replication of a register or a LUT driving a net by adding the FORCE_MAX_FANOUT property to the net. The value of the FORCE_MAX_FANOUT specifies the maximum physical fanout the nets should have after the replication optimization. The physical fanout in this case refers to the actual site pin loads, not the logical loads. For example, if the replica drives multiple LUTRAM loads that are all grouped in the same slice, the combined fanout is 1 for all of the LUTRAMs in the same slice.

The FORCE_MAX_FANOUT property forces the replication during physical synthesis regardless of the slack of the signal. You can force replication based on physical device attributes with the MAX_FANOUT_MODE property. The property can take on the value of CLOCK_REGION, SLR, or MACRO.

For example, the MAX_FANOUT_MODE property with a value of CLOCK_REGION replicates the driver based on the physical clock region. The loads placed into same clock region are clustered together. The MAX_FANOUT_MODE property takes precedence over the FORCE_MAX_FANOUT property, and physical synthesis attempts to honor both properties by applying MAX_FANOUT_MODE optimization first. Its replicated drivers then inherit the FORCE_MAX_FANOUT property to do further replication within a clock region.

This is shown in the following figure, where a register drives four loads: two registers and two MACRO loads (block RAM, UltraRAM, or DSP). Replication provides separate drivers for the register loads and MACRO loads. The driver for the MACRO loads is then replicated until the FORCE_MAX_FANOUT property value is satisfied.

Figure 2. Applying MAX_FANOUT_MODE with Value MACRO with FORCE_MAX_FANOUT

Note: This optimization happens early in the placer. In the later stages of the placer as the timing accuracy improves, both the replicated source and/or load registers may be moved to different clock regions or SLRs if the timing estimate improves.

DSP Register Optimization

DSP Register Optimization can move registers out of the DSP cell into the logic array or from logic to DSP cells if it improves the delay on the critical path.

Shift Register to Pipeline Optimization

Shift Register to Pipeline Optimization turns a shift register with fixed length greater than 1 to a dynamically adjusted register pipeline. It pulls more registers when the distance to cover is longer. The registers are placed optimally to balance timing paths. The latency is unaffected.

Only SRLs with the PHYS_SRL2PIPELINE attribute set to TRUE are considered for this optimization. The property must be set on the SRL cell and should be set on all bits of a bus to have all the bits optimized. The pull of FFs happens on the SRL's Q-pin.

Block RAM Register Optimization

Block RAM Register Optimization can move registers out of the block RAM cell into the logic array or from logic to block RAM cells if it improves the delay on the critical path.

URAM Register Optimization

UltraRAM Register Optimization can move registers out of the UltraRAM cell into the logic array or from logic to UltraRAM cells if it improves the delay on the critical path.

Dynamic/Static Region Interface Net Replication

Optimization to replicate drivers on static design to reconfigurable module boundary paths in DFX flow.

Equivalent Driver Rewire Optimization

This optimization redistributes loads between logically-equivalent drivers to minimize routing overlap and provide a more optimal co-location of drivers and loads. This helps reduce utilization and congestion and allows later placer stages to move drivers and loads more optimally to improve QoR.

Physical Optimization of SLR crossings

The physical optimization of SLR crossing pulls out registers from the SRL if there is an SLR crossing. It guides the tool to have an optimal FF->FF SLR crossing to increase the performance on the SLR crossing by using the USER_SLL_REG=TRUE property. If, after the optimization, the SRL depth becomes one, it is converted into a regular register.

The optimization occurs when:

• Fanout of the SRL is 1
• Minimum clock frequency threshold is 250 MHz
• SRL needs to have a minimum depth of 2
• SRL is not LUT combined
• Source and destination cells are in neighboring SLRs

Supported circuits:

1. SRL → SLR Crossing → BRAM/URAM/DSP
2. SRL → FF → SLR Crossing → BRAM/URAM/DSP
3. SRL → SLR Crossing → FF → BRAM/URAM/DSP
4. BRAM/URAM/DSP→ SLR Crossing → SRL
5. BRAM/URAM/DSP→ FF → SLR Crossing → SRL
6. BRAM/URAM/DSP→ SLR Crossing → FF → SRL
7. LUT→ SLR Crossing → SRL
8. SRL→ SLR Crossing → LUT

Example:

For more information on these optimizations see Available Physical Optimizations in the Physical Optimization section. Physical synthesis in the placer is run by default in all of the placer directives. At the end of the physical synthesis phase, a table shows the summary of optimizations.

When an optimization is performed on a primitive cell, the PHYS_OPT_MODIFIED property of the cell is updated to reflect the optimizations performed on the cell. When multiple optimizations are performed on the same cell, the PHYS_OPT_MODIFIED value contains a list of optimizations in the order they occurred. The following table lists the PHYS_OPT_MODIFIED and PHYS_OPT_SKIPPED values that correspond with a Physical Synthesis optimization.