For Versal devices, a Multi-Clock Buffer (MBUFG) provides divide by 1, 2, 4, 8 clocks of the clock input on its O1, O2, O3, and O4 outputs. The MBUFG buffer routes the full-speed clock using a single global clock resource, and divides by 2, 4, or 8 as needed using local resources near the destination loads. MBUFG driven clocks consume fewer global routing resources. Clock skew is minimized for synchronous CDC paths between clocks driven by the same MBUFG because the common node is closer to the source and destination.
The MBUFG optimization replaces parallel clock buffers driven by a common driver or clock modifying block (CMB), such as MMCM, DPLL, or XPLL with a single MBUFG. The transformation occurs when the parallel clocks are derived from a common clock using divide ratios of 1, 2, 4, or 8, and when each clock buffer drives more than 50 loads. For CMB driven clocks, the phase shift has to be 0 and the duty cycle 50%. The MBUFG optimization is skipped when parallel buffers have conflicting clock constraints such as CLOCK_DELAY_GROUP or USER_CLOCK_ROOT, or when optimization would lose the original timing constraint intent. The following topologies are supported:
- Parallel BUFGCEs connected to a CMB are converted to an MBUFGCE.
- Parallel BUFGCE_DIVs connected to a common clock driver are converted to an MBUFGCE.
- Parallel BUFG_GTs connected to a common clock driver are converted to an MBUFG_GT.
In addition to the global optimization using the -mbufg_opt
option, you can control the conversion of selected BUFGs to MBUFG using the
MBUFG_GROUP property. You must set the MBUFG_GROUP constraint on the net segment
directly connected to the clock buffer. The following example shows the property
applied to two clock nets, which are directly driven by the clock buffers:
set_property MBUFG_GROUP grp1 [get_nets -of [get_pins {BUFG_inst_0/O BUFG_inst_1/O}]The picture in the following figure shows an MMCM driving several BUFGCE buffers. The CLKOUTn driven clocks are integer divisions of 1, 2, 4, 8 of the CLKOUT1 driven clock. After the MBUFG optimization the four BUFGCEs are transformed to a single MBUFGCE and the CLKOUT1 driven clock is connected to the MBUFGCE I pin. The loads that were driven by the BUFGCEs are connected to the MBUFGCE O1, O2, O3, and O4 pins.