The Vivado Design Suite supports netlist-driven design by importing previously synthesized netlists from AMD or third-party tools. The netlist input formats include:
- Structural Verilog
- Structural SystemVerilog
- EDIF
- AMD NGC
- Synthesized Design Checkpoint (DCP)
Important:
Vivado Design Suite does not support NGC format files for UltraScale and later devices. Regenerate the IP using the
Vivado Design Suite IP customization tools with
native output products. Alternatively,
convert_ngc Tcl
utility to convert NGC files to EDIF or Verilog formats. However, AMD recommends using native Vivado IP rather than XST-generated NGC format files going
forward.Important: When using IP in Project
Mode or Non-Project Mode, always use the XCI file and not the DCP file. This ensures
consistent use of IP output products throughout the design flow. If the IP was
synthesized out of context and has an associated DCP, Vivado
automatically uses it and does not re-synthesize the IP.
For more information, see section Adding Existing IP to a Project in the Vivado Design Suite User Guide: Designing with IP (UG896).
For more information on the source files and project types supported by the Vivado Design Suite, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895).