Implementation Strategies (Versal) - Implementation Strategies (Versal) - 2026.1 English - UG904

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2026-06-23
Version
2026.1 English
Table 1. Implementation Strategy Description
Implementation Strategy Name Description
Vivado Advanced Implementation Defaults Default settings for Advanced Implementation.
Performance_Explore Uses multiple algorithms for optimization, placement, and routing to get potentially better results.
Performance_AggressiveExplore Higher effort version of Explore algorithms.
Performance_ExplorePostRoutePhysOpt Similar to Peformance_Explore, but enables the physical optimization step (phys_opt_design) with the Explore directive after routing.
Performance_ExploreWithRemap Similar to Performance_ExplorePostRoutePhysOpt, but enables logic optimization step (opt_design) with the ExploreWithRemap directive.
Performance_WLBlockPlacement Minimize wirelength of connections to RAM and DSP blocks.
Performance_EarlyBlockPlacement Place RAM and DSP blocks in Global Placement.
Performance_NetDelay_high To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. (high setting, most pessimistic)
Performance_NetDelay_medium To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections. medium setting, more pessimistic)
Performance_Retiming Combines retiming in phys_opt_design with extra placement optimization and higher router delay cost.
Performance_ExtraTimingOpt Includes alternate algorithms for timing-driven optimization
Performance_BalanceSLRs A placement variation for SSI devices to balance logic packing between SLRs.
Performance_HighUtilSLRs A placement variation for SSI devices with more logic packing in each SLR.
Congestion_SpreadLogic_high Spread logic throughout the device to avoid creating congested regions. (high setting: highest degree of spreading)
Congestion_SpreadLogic_medium Spread logic throughout the device to avoid creating congested regions. (medium setting)
Congestion_SSI_SpreadLogic_high Spread logic throughout SSI device to avoid creating congested regions. (high setting: highest degree of spreading)
Congestion_SSI_SpreadLogic_medium Spread logic throughout SSI device to avoid creating congested regions. (medium setting: some spreading)
Area_Explore Uses multiple optimization algorithms to get potentially fewer LUTs.
Area_ExploreSequential Uses multiple optimization algorithms to get potentially fewer LUTs and registers.
Area_ExploreWithRemap Adds the remap optimization to reduce logic
Flow_RuntimeOptimized Each implementation step trades design performance for better runtime. Physical optimization (phys_opt_design) is disabled.
Flow_Quick Fastest possible runtime, all timing-driven behavior disabled. Useful for utilization estimation.
Table 2. Directives and Switches Used by opt_design and place_design in Implementation Strategies
Strategy opt_design Directive place_design Directive Subdirectives and Switches
Vivado Advanced Implementation Defaults Default Default N/A
Performance_Explore Explore Explore N/A
Performance_AggressiveExplore Explore AggressiveExplore N/A
Performance_ExplorePostRoutePhysOpt Explore Explore N/A
Performance_ExploreWithRemap ExploreWithRemap Explore N/A
Performance_WLBlockPlacement Explore Explore Floorplan.WLDrivenBlockPlacement GPlace.WLDrivenBlockPlacement
Performance_EarlyBlockPlacement Explore Explore GPlace.EarlyBlockPlacement
Performance_NetDelay_high Explore Explore N/A
Performance_NetDelay_medium Explore Explore N/A
Performance_Retiming Explore Explore N/A
Performance_ExtraTimingOpt Explore Explore Floorplan.ExtraTimingUpdate Floorplan.ExtraTimingOpt.high GPlace.ExtraTimingUpdate GPlace.ExtraTimingOpt.high DPlace.ExtraTimingUpdate DPlace.ExtraTimingOpt.high
Performance_BalanceSLRs Explore Explore Floorplan.BalancedSLR.high
Performance_HighUtilSLRs Explore Explore Floorplan.BalancedSLR.low
Congestion_SpreadLogic_high Default Default Floorplan.ForceSpreading.high GPlace.ForceSpreading.high GPlace.ReduceCongestion.high DPlace.ReducePinDensity.high
Congestion_SpreadLogic_medium Default Default Floorplan.ForceSpreading.med GPlace.ForceSpreading.med GPlace.ReduceCongestion.med DPlace.ReducePinDensity.med
Congestion_SSI_SpreadLogic_high Default Default Floorplan.BalancedSLR.high
Congestion_SSI_SpreadLogic_medium Default Default Floorplan.BalancedSLR.med
Area_Explore ExploreArea Default N/A
Area_ExploreSequential ExploreSequentialArea Default N/A
Area_ExploreWithRemap ExploreWithRemap Default N/A
Flow_RuntimeOptimized RuntimeOptimized RuntimeOptimized N/A
Flow_Quick RuntimeOptimized Quick N/A
Table 3. Directives Used by phys_opt_design and route_design in Implementation Strategies
Strategy phys_opt_design Directive route_design Directive
Vivado Advanced Implementation Defaults Default Default
Performance_Explore Explore Explore
Performance_AggressiveExplore AggressiveExplore AggressiveExplore
Performance_ExplorePostRoutePhysOpt Explore Explore
Performance_ExploreWithRemap Explore NoTimingRelaxation
Performance_WLBlockPlacement Explore NoTimingRelaxation
Performance_EarlyBlockPlacement Explore NoTimingRelaxation
Performance_NetDelay_high AggressiveExplore NoTimingRelaxation
Performance_NetDelay_medium AggressiveExplore NoTimingRelaxation
Performance_Retiming AlternateFlowWithRetiming Explore
Performance_ExtraTimingOpt Explore NoTimingRelaxation
Performance_BalanceSLRs Explore Explore
Performance_HighUtilSLRs Explore Explore
Congestion_SpreadLogic_high AggressiveExplore AlternateCLBRouting
Congestion_SpreadLogic_medium Explore AlternateCLBRouting
Congestion_SSI_SpreadLogic_high AggressiveExplore AlternateCLBRouting
Congestion_SSI_SpreadLogic_medium AggressiveExplore AlternateCLBRouting
Area_Explore Default Default
Area_ExploreSequential Default Default
Area_ExploreWithRemap Default Default
Flow_RuntimeOptimized Default RuntimeOptimized
Flow_Quick Default Quick