Clock Optimization - Clock Optimization - 2026.1 English - UG904

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2026-06-23
Version
2026.1 English

By default, clock optimization in Physical Optimization is path-based. This approach focuses on optimizing specific paths within a design. It is useful for improving the timing of critical paths and allows incremental timing updates after each optimization to assess the impact on design performance.

Phase-based clock optimization can be enabled through the -clock_opt switch. Phase-based clock optimization divides the optimization process into distinct phases, each targeting different aspects of the design, such as specific block types like URAM, Block RAM, and DSP to take advantage of useful clock skew. It enhances the optimization of paths to these block types by leveraging clock skew, particularly using CLK_MODs in IRI_QUADs to improve negative setup slack. In some designs, there might not be enough output slack available to effectively borrow during this optimization process.