For Versal designs, there is a dedicated buffer to use the clock tree network for non-clock pins called BUFG_FABRIC. BUFG_FABRIC cells are inserted during opt_design to drive high fanout nets (HFN) with more than 25,000 logical loads. For SSI designs, if loads of a BUFG_FABRIC global buffer span multiple SLRs, the BUFG_FABRIC is replicated in each SLR so that each replica only drives loads within a single SLR. This reduces the overall high-fanout net delay. This replication occurs before clock placement to ensure that each BUFG_FABRIC resource is counted against the available global clock buffer resources, thereby avoiding global clock buffer overutilization in placement. Depending on the clock utilization, these cells are replicated once again towards the end of placer during the BUFG_FABRIC Optimization phase to driver loads located in a single common clocking column partition of each SLR leading to further QoR enhancements. Furthermore, nets that were not previously promoted to BUFG_FABRIC by opt_design are opportunistically targeted by placer.