BUFG Optimization (Default) - BUFG Optimization (Default) - 2026.1 English

BUFG Optimization (Default) - BUFG Optimization (Default) - 2026.1 English - UG904

Vivado Design Suite User Guide: Implementation (UG904)

Document ID

UG904

Release Date

2026-06-23

Version

2026.1 English

Logic optimization conservatively inserts global clock buffers on clock nets and high-fanout non-clock nets such as device-wide resets. In Versal devices, BUFG_FABRIC clock buffers are inserted on high-fanout non-clock nets.

For 7 series designs, clock buffers are inserted as long as 12 total global clock buffers are not exceeded.

For UltraScale, UltraScale+, and Versal designs, clock buffers are inserted as long as 24 total global clock buffers are not exceeded, not including BUFG_GT buffers.

For non-clock nets, check the following:

The fanout must be above 25,000.
The clock period of the logic driven by the net is below a device/speed grade specific limit.

For fabric-driven clock nets, the fanout must be 30 or greater.

For Versal designs, PS clock pins driving PL logic require BUFG_PS buffering. All remaining BUFG insertions default to BUFG_FABRIC, because these are the only PS‑side clocks that necessitate the PS‑specific buffer. For example, if a PS clock pin driving fabric logic has BUFGCE, it is retargeted to BUFG_FABRIC.

Note: To prevent BUFG Optimization on a net, assign the value NONE to the CLOCK_BUFFER_TYPE property of the net. Some clock buffer insertion that is required to legalize the design can also occur in mandatory logic optimization.