You can add constraints to HDL sources as attribute statements. Add attributes to both Verilog and VHDL sources to pass through to Vivado synthesis or Vivado implementation.
In some cases, constraints are available only as HDL attributes, and are not available in XDC. In those cases, the constraint must be specified as an attribute in the HDL source file. For example, define Relatively Placed Macros (RPMs) using HDL attributes. An RPM is a set of logic elements (such as FF, LUT, DSP, and RAM) with relative placements.
You can define RPMs using U_SET and HU_SET attributes
and define relative placements using Relative Location Attributes.
For more information about Relative Location Constraints, see section Migrating UCF Constraints to XDC in the Vivado Design Suite User Guide: Using Constraints (UG903).
For more information on constraints that XDC does not support, see the ISE to Vivado Design Suite Migration Guide (UG911).