set_bus_skew Example Two - set_bus_skew Example Two - 2026.1 English - UG903

In this example, the CDC is on a gray‑coded bus. The system must ensure that only one transition of the gray‑coded bus is captured by the destination clock domain at the same time.

If the source clock period is 5 ns and the destination clock period is 2.5  ns, set the bus skew on the CDC path to 2.5  ns (destination clock period).

set_bus_skew -from [get_cells src_gray_ff_reg*] -to [get_cells {dest_graysync_ff_reg[0]*}] 2.500

Figure 1. set_bus_skew Example Two

For completeness, add a set_max_delay constraint to ensure the source and destination registers are not placed too far apart.

In this case, set the maximum delay to the source clock period because the CDC is from a slower clock to a faster clock, and only one bus transition should be captured by the destination clock domain.

set_max_delay -datapath_only \
           -from [get_cells src_gray_ff_reg*] \
           -to [get_cells {dest_graysync_ff_reg[0]*}] 5.000