set_bus_skew Example Two - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

In this example, the CDC is on a gray-coded bus. The system must ensure that only one transition of the gray-coded bus is captured by the destination clock domain at the same time.

If the source clock period is 5 ns and the destination clock period is 2.5 ns, the bus skew on the CDC path should be set to 2.5 ns (destination clock period).

set_bus_skew -from [get_cells src_gray_ff_reg*] -to [get_cells {dest_graysync_ff_reg[0]*}] 2.500
Figure 1. set_bus_skew Example Two

Note: For completeness, the CDC needs an additional set_max_delay constraint to ensure that the source and destination registers are not placed too far apart. In this case, the max delay is set to the source clock period as the CDC is between a slower clock to a faster clock and only one transition of the bus should be captured by the destination clock domain:
set_max_delay -datapath_only -from [get_cells src_gray_ff_reg*] -to [get_cells
{dest_graysync_ff_reg[0]*}] 5.000