In this example, the CDC is part of a handshake mechanism. The source clock domain generates a send signal when data is ready to sample. The destination clock domain synchronizes the send signal using a four‑stage synchronizer.
After synchronization, the signal drives the clock‑enable pin of the CDC destination registers. In clock‑enabled control CDC structures, adjust bus skew to match the number of CE stages. This number represents destination clock cycles during which the data is valid.
If the source clock period is 5 ns and the destination clock period is 2.5
ns, set the bus skew to 10 ns (4 × 2.5
ns).
set_bus_skew -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] 10.000Figure 1. set_bus_skew Example One
Note: For completeness, add a
set_max_delay
constraint to ensure that the source and destination registers are not placed too
far apart. Following is an example of a maximum‑delay constraint:
set_max_delay -datapath_only -from [get_cells src_hsdata_ff_reg*] -to [get_cells dest_hsdata_ff_reg*] 10.000