Virtual Clocks - Virtual Clocks - 2026.1 English - UG903

A virtual clock is not attached to any netlist element in the design. Define a virtual clock with create_clock and omit a source object. Use a virtual clock to specify input and output delay constraints when the following happens:

A virtual clock is commonly used to specify input and output delay constraints in one of the following situations:

• The external device I/O reference clock is not a design clock.
• The FPGA I/O paths relate to internally generated clock that cannot be properly timed against the board clock from which it is derived.
  Note: This occurs when the period ratio between the two periods is non-integer, creating unrealistic requirements.
• You need different jitter and latency only for the I/O delay reference, without changing internal clocks.

For example, clk_virt has a 10 ns period and no attached netlist object. Omit the [<objects>] argument; -name is mandatory.

create_clock -name clk_virt -period 10

Define virtual clocks before using them with input and output delay constraints.