Virtual Clocks - 2024.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2024-06-15
Version
2024.1 English

A virtual clock is a clock that is not physically attached to any netlist element in the design.

A virtual clock is defined by means of the create_clock command without specifying a source object.

A virtual clock is commonly used to specify input and output delay constraints in one of the following situations:

  • The external device I/O reference clock is not one of the design clocks.
  • The FPGA I/O paths are related to an internally generated clock that cannot be properly timed against the board clock from which it is derived.
    Note: This happens when the ratio between the two periods is not an integer. which leads to a very tight and unrealistic timing path requirement.
  • You want to specify different jitter and latency only for the clock related to the I/O delay constraints without modifying the internal clocks characteristics.

For example, the clock clk_virt has a period of 10 ns and is not attached to any netlist object. The [<objects>] argument is not specified. The -name option is mandatory in such cases.

create_clock -name clk_virt -period 10

The virtual clocks must be defined before being used by the input and output delay constraints.