Valid Commands in an XDC File - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English
Table 1. Valid Commands in an XDC File
Timing Constraint Physical Constraint General Purpose
create_clock

create_generated_clock

group_path

set_clock_groups

set_clock_latency

set_data_check

set_disable_timing

set_false_path

set_input_delay

set_output_delay

set_max_delay

set_min_delay

set_multicycle_path

set_case_analysis

set_clock_sense

set_clock_uncertainty

set_input_jitter

set_max_time_borrow

set_propagated_clock

set_system_jitter

set_external_delay

set_bus_skew

add_cells_to_pblock

create_pblock

delete_pblock

remove_cells_from_pblock

resize_pblock

create_macro

delete_macros

update_macro

set_package_pin_val

set

expr

list

filter

current_instance

get_hierarchy_separator

set_hierarchy_separator

get_property

set_property

set_units

endgroup

startgroup

create_property

current_design

Debug Constraint
create_debug_core

create_debug_port

connect_debug_port

Power Constraint Netlist Constraint

set_power_opt

set_switching_activity

reset_switching_activity

set_operating_conditions

reset_operating_conditions

add_to_power_rail

create_power_rail

delete_power_rails

get_power_rails

remove_from_power_rail

set_load

set_logic_dc

set_logic_one

set_logic_zero

set_logic_unconnected

make_diff_pair_ports

Waiver Constraint
create_waiver
Device Object Query Timing Object Query Netlist Object Query
get_iobanks all_clocks all_cpus
get_package_pins get_path_groups all_dsps
get_sites get_clocks all_fanin
get_bel_pins get_generated_clocks all_fanout
get_bels get_timing_arcs all_hsios
get_nodes get_speed_models all_inputs
get_pips Floorplan Object Query all_outputs
get_site_pins all_rams
get_pblocks
get_site_pips get_macros all_registers
get_slrs all_ffs
get_tiles all_latches
get_wires get_cells
get_pkgpin_bytegroups get_nets
get_pkgpin_nibbles get_pins
get_ports
get_debug_cores
get_debug_ports