Although the -clock option is optional in the SDC standard, it is
required by the Vivado Design Suite tools.
The relative clock can either be a design clock or a virtual clock.
Recommended: When using a virtual clock, use the same
waveform as the design clock related to the output ports inside the design. This way,
the timing path requirement is realistic. Using a virtual clock is convenient for
modeling jitter or source latency scenarios without modifying the design clock.
The Output Delay command options are: