Although the -clock option is optional in the
Synopsys design constraints (SDC) standard, Vivado IDE
requires it. Use a design clock or a virtual clock as the relative clock.
Recommended: When using a virtual clock, match
its waveform to the related design clock at the interface. This keeps timing path
requirements realistic. A virtual clock also lets you model different jitter or
source‑latency scenarios without modifying the design clock.
The input delay command options are as follows: