Although the -clock option is optional in the Synopsys Design
Constraints (SDC) standard, it is required by the Vivado IDE. The
relative clock can be either a design clock or a virtual clock.
Recommended: When using a virtual clock, use the same
waveform as the design clock related to the input ports inside the design. This way, the
timing path requirement is realistic. Using a virtual clock is convenient for modeling
different jitter or source latency scenarios without modifying the design clock.
The Input Delay command options are: