Use these examples to apply set_output_delay
correctly. For more methodology, refer to Constraining Input and Output Ports in the
UltraFast Design Methodology Guide for FPGAs and SoCs
(UG949).
Output Delay Example One
Define an output delay relative to a previously defined sysClk
for both minimum and maximum analysis.
create_clock -name sysClk -period 10 [get_ports CLK0]
set_output_delay -clock sysClk 6 [get_ports DOUT]Output Delay Example Two
Define an output delay relative to a previously defined virtual clock.
create_clock -name clk_port_virt -period 10
set_output_delay -clock clk_port_virt 6 [get_ports DOUT]Output Delay Example Three
Specify output delay relative to a DDR clock with different values for minimum (hold) and maximum (setup).
create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_output_delay -clock clk_ddr -max 2.1 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -max 1.9 [get_ports DDR_OUT] -clock_fall -add_delay
set_output_delay -clock clk_ddr -min 0.9 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -min 1.1 [get_ports DDR_OUT] -clock_fall -add_delayThese constraints model data launched on both clock edges outside the device to an internal flip-flop sensitive to both edges.
Output Delay Example Four
Specify the clock and output delay on STARTUPE3 internal pins (UltraScale+ devices) to time paths from the fabric to STARTUPE3.
create_generated_clock -name clk_sck -source [get_pins -hierarchical
*axi_quad_spi_0/ext_spi_clk] [get_pins STARTUP/CCLK] -edges {3 5 7}
set_output_delay -clock clk_sck -max 6 [get_pins STARTUP/DATA_OUT[*]]
set_output_delay -clock clk_sck -min 1 [get_pins STARTUP/DATA_OUT[*]]