Use of set_input_delay Command Options - Use of set_input_delay Command Options - 2026.1 English - UG903

The following examples show typical uses of set_input_delay. For more methodology, refer to Constraining Input and Output Ports in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

Input Delay Example One

This example defines an input delay relative to previously defined sysClk for both min and max analyses.

create_clock -name sysClk -period 10 [get_ports CLK0]
set_input_delay -clock sysClk 2 [get_ports DIN]

Input Delay Example Two

This example defines an input delay relative to a previously defined virtual clock.

create_clock -name clk_port_virt -period 10
set_input_delay -clock clk_port_virt 2 [get_ports DIN]

Input Delay Example Three

This example defines different input delay values for min and max analyses relative to sysClk.

create_clock -name sysClk -period 10 [get_ports CLK0]
set_input_delay -clock sysClk -max 4 [get_ports DIN]
set_input_delay -clock sysClk -min 1 [get_ports DIN]

Input Delay Example Four

To constrain pure combinational paths between I/O ports, define input and output delay relative to a previously defined virtual clock.

The example below sets a 5 ns (10 ns − 4 ns − 1 ns) requirement between ports DIN and DOUT.

create_clock -name sysClk -period 10
set_input_delay -clock sysClk 4 [get_ports DIN]
set_output_delay -clock sysClk 1 [get_ports DOUT]

Refer to Combinational Delays for constraining combinational paths using the Timing Constraints Wizard.

Input Delay Example Five

This example specifies input delay relative to a DDR clock.

create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_input_delay -clock clk_ddr -max 2.1 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -max 1.9 [get_ports DDR_IN] -clock_fall -add_delay
set_input_delay -clock clk_ddr -min 0.9 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -min 1.1 [get_ports DDR_IN] -clock_fall -add_delay

These constraints model data launched on both clock edges outside the device to an internal flip-flop sensitive to both edges.

Input Delay Example Six

This example specifies the clock and input delay on STARTUPE3 internal pins (AMD UltraScale+™ devices) to time the paths from STARTUPE3 to the fabric.

create_generated_clock -name clk_sck -source [get_pins -hierarchical*axi_quad_spi_0/ext_spi_clk] [get_pins STARTUP/CCLK] -edges {3 5 7}
set_input_delay -clock clk_sck -max 7 [get_pins STARTUP/DATA_IN[*]] -clock_fall
set_input_delay -clock clk_sck -min 1 [get_pins STARTUP/DATA_IN[*]] -clock_fall

For more information on timing constraints for STARTUPE3, refer to the AXI Quad SPI LogiCORE IP Product Guide (PG153).