Timing Constraints Wizard - Timing Constraints Wizard - 2026.1 English - UG903

The Timing Constraints Wizard identifies missing timing constraints on a synthesized or implemented design. It analyzes the netlist, clock net connectivity, and existing timing constraints. The tool provides recommendations based on the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

The wizard covers three categories of constraints across 11 pages, followed by a summary.

• Clocks
  • Primary clocks
  • Generated clocks
  • Forwarded clocks
  • External feedback delays
• Input and output ports
  • Input delays
  • Output delays
  • Combinatorial delays
• Clock domain crossing
  • Physically exclusive clock groups
  • Logically exclusive clock groups with no interaction
  • Logically exclusive clock groups with interaction
  • Asynchronous clock domain crossings
• Constraints summary

During each step, you can accept the recommended constraints or modify the list by checking or unchecking the proposed items. Unchecking recommended constraints early can prevent the wizard from identifying other missing constraints later.

For example, if you skip creating a clock, the wizard does not identify or recommend related constraints. This includes constraints referencing that clock or its auto-derived clocks.

The final page of the wizard summarizes the constraints it creates. You can click each hyperlink to view constraint details. After exiting the wizard, you can also visualize new constraints in the Timing Constraints window.

Optional reports include the following:

Create Timing Summary report

Shows timing slack with the new constraints and runs check_timing. Timing violations can occur if the period or I/O delay constraints are too tight.

Create Check Timing report

Identifies missing or inappropriate constraints by running check_timing.

Create DRC Report using only Timing Checks

Runs only timing design rule checks (DRCs).

The wizard does not recommend constraints that can introduce unsafe timing analysis. It also does not fix inappropriate constraints already present when loading the design. Some invalid constraints can become valid after creating all missing clocks in project mode. For more details, refer to Constraints Processing Order and Invalid Constraints.

If check_timing or report_drc still show constraint issues after using the wizard, the problem likely comes from existing source XDC files. Address these issues directly instead of relying on the wizard.