System Jitter - System Jitter - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

System jitter is the overall jitter from power-supply noise, board noise, or any extra system jitter. Use set_system_jitter to set a single value for the entire design.

The following command sets ±100 ps input jitter on the primary clock propagating through input port clkin:

set_input_jitter [get_clocks -of_objects [get_ports clkin]] 0.1
Note: The timing engine does not use a single equation for clock uncertainty. It computes uncertainty per path based on the clocking topology, the clock pair, the presence of an MMCM/PLL on the tree, and other factors. The Report Timing text and GUI show the breakdown of clock uncertainty for each timing path.