System Jitter - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

System jitter is the overall jitter due to power supply noise, board noise, or any extra jitter of the system.

Use the set_system_jitter command to set only one value for the whole design, that is, all the clocks.

The following command sets a +/-100 ps jitter on the primary clock propagating through input port clkin:

set_input_jitter [get_clocks -of_objects [get_ports clkin]] 0.1
Note: The impact of input jitter and system jitter in the overall calculation of the clock uncertainty is not trivial and does not follow a single equation. The calculation of the clock uncertainty is path-dependent and depends on the clocking topology, the clock-pair involved in the path, the presence or not of an MMCM/PLL on the clock tree, and other considerations. However, the text and GUI of the Report Timing command expose the breakdown of the clock uncertainty for each timing path.