Synthesis and Implementation Constraint Files - Synthesis and Implementation Constraint Files - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2026-07-01
Version
2026.1 English

By default, the Vivado IDE uses all XDC files and Tcl scripts in a constraint set for both synthesis and implementation. Set the USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION properties on an XDC file or Tcl script to change this behavior. Assign each property a value of TRUE or FALSE.

Important: The DONT_TOUCH attribute does not follow the USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION properties. If you apply DONT_TOUCH properties in the synthesis XDC, they propagate to implementation, regardless of the value assigned to USED_IN_IMPLEMENTATION. Refer to RTL Attributes for more information about the DONT_TOUCH attribute.
Important: When you synthesize any module, such as IP or BD, in OOC mode, the top-level synthesis run infers a black box for that module. Top-level synthesis constraints cannot reference pins, nets, or cells inside an OOC module. If constraints reference objects inside an OOC module, split them into two files. Create one XDC file for synthesis with USED_IN_SYNTHESIS=TRUE and USED_IN_IMPLEMENTATION=FALSE. Create another XDC file for implementation with USED_IN_SYNTHESIS=FALSE and USED_IN_IMPLEMENTATION=TRUE. No such limitation exists during implementation because netlists from OOC module DCPs are linked with the netlist generated from top-level design synthesis. Vivado Design Suite resolves black boxes during implementation, applying XDC output products and user constraints.
Important: When writing XDC constraints for elements inside a protected IP, use non-protected, non-obfuscated names in project constraint sets. The same applies when opening XDC files with read_xdc or open_checkpoint. However, when applying constraints through the Tcl Console or unmanaged XDC files, use the protected, obfuscated names for design elements in those constraints.

For example, follow these instructions to use a constraint file for implementation only.

  1. Select the constraint file in the Sources window.
  2. In the Source File Properties window:
    1. Clear Synthesis.
    2. Select Implementation.


The equivalent Tcl commands are as follows:

set_property USED_IN_SYNTHESIS false [get_files wave_gen_pins.xdc]
set_property USED_IN_IMPLEMENTATION true [get_files wave_gen_pins.xdc]

When running Vivado in non-project mode, you can read in the constraints directly between any steps of the flow. In this mode, the properties USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION do not apply.

The following compilation Tcl script demonstrates how to read two XDC files for different steps of the flow:

read_verilog [glob src/*.v] 
read_xdc wave_gen_timing.xdc
synth_design -top wave_gen -part xc7k325tffg900-2 
read_xdc wave_gen_pins.xdc
opt_design 
place_design 
route_design
Table 1. Reading XDC Files Before and After Synthesis
File Name File Placement Used For
wave_gen_timing.xdc Before synthesis
  • Synthesis
  • Implementation
wave_gen_pins.xdc After synthesis Implementation
Tip: The tool applies constraints read after synthesis alongside those read before synthesis.