Syntax for Defining RPM Sets in Verilog - Syntax for Defining RPM Sets in Verilog - 2026.1 English

Syntax for Defining RPM Sets in Verilog - Syntax for Defining RPM Sets in Verilog - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID

UG903

Release Date

2026-07-01

Version

2026.1 English

Define RPM sets as attributes in Verilog using the following syntax.

U_SET Example

(* U_SET = "uset0", RLOC = "X0Y0" *) FD my_reg (.C(clk), .D(d0), .Q(q0));

HU_SET Example

(* HU_SET = "huset0", RLOC = "X0Y0" *) FD other_reg (.C(clk), .D(d1), .Q(q1));

Recommended: When you use H_SET and HU_SET RPMs with Vivado synthesis, preserve the hierarchical boundary of the module or instance that contains the RPMs. Preserving the hierarchy avoids naming collisions between RPMs at the same hierarchical level when the hierarchy dissolves. For more information on hierarchy preservation, refer to the Vivado Design Suite User Guide: Synthesis (UG901).