Supported SDC Commands - Supported SDC Commands - 2026.1 English

Note: All AMD Tcl commands support the -quiet and -verbose options. The following table does not list these options.

Table 1. Supported SDC Commands
SDC 1.9	AMD SDC	Notes
`current_instance` `[<instance_name>]`	`current_instance` `[<instance_name>]`	The Vivado IDE handles get_ports differently when you use `read_xdc -cells/-ref` or the `SCOPED_TO_xxx` constraint file property.
`expr`	`expr`
`list`	`list`	In the Vivado IDE, you also use a Tcl list as a container for objects.
`set`	`set`
`set_hierarchy_separator` `[<separator>]`	`set_hierarchy_separator` `[<separator>]`
`set_units` `[-capacitance <cap_units>]` `[-resistance <res_unit>]` `[-time <time_unit>]` `[-voltage <voltage_units>]` `[-current <current_unit>]` `[-power <power_unit>]`	`set_units` `[-capacitance <arg>]` `[-resistance <arg>]` `[-time <arg>]` `[-voltage <arg>]` `[-current <arg>]` `[-power <arg>]` `[-suffix <arg>]` `[-digits <arg>]`	You cannot change the timing unit in the Vivado IDE with `set_units -time`.
`all_clocks`	`all_clocks`
`all_inputs` `[-level_sensitive]` `[-edge_triggered]` `[-clock <clock_name>]`	`all_inputs`
`all_outputs` `[-level_sensitive]` `[-edge_triggered]` `[-clock <clock_name>]`	`all_outputs`
`all_registers` `[-no_hierarchy]` `[-clock <clock_name>]` `[-rise_clock <clock_name>]` `[-fall_clock <clock_name>]` `[-cells]` `[-data_pins]` `[-clock_pins]` `[-slave_clock_pins]` `[-async_pins]` `[-output_pins]` `[-level_sensitive]` `[-edge_triggered]` `[-master_slave]`	`all_registers` `[-no_hierarchy]` `[-clock <args>]` `[-rise_clock <args>]` `[-fall_clock <args>]` `[-cells]` `[-data_pins]` `[-clock_pins]` `[-async_pins]` `[-output_pins]` `[-level_sensitive]` `[-edge_triggered]`
`current_design`	`current_design`	In the Vivado IDE, the current design refers to the design loaded in memory. You cannot change it to another module or entity other than the top level.
`get_cells` `[-hierarchical]` `[-hsc <separator>]` `[-regexp]` `[-nocase]` `-of_objects <objects>` `<patterns>`	`get_cells` `[-hierarchical]` `[-hsc <arg>]` `[-regexp]` `[-nocase]` `[-of_objects <args>]` `[<patterns>]` `[-filter <arg>]` `[-match_style <arg>]`
`get_clocks` `[-regexp]` `[-nocase]` `<patterns>`	`get_clocks` `[-regexp]` `[-nocase]` `[<patterns>]` `[-filter <arg>]` `[-of_objects <args>]` `[-match_style <arg>]` `[-include_generated_clocks]`	In the Vivado IDE, you can use the `-of_objects` option to query the clock object on the clock tree.
`get_lib_cells` `[-hsc <separator>]` `[-regexp]` `[-nocase]` `<patterns>`	`get_lib_cells` `[-regexp]` `[-nocase]` `<patterns>` `[-filter <arg>]` `[-include_unsupported]` `[-of_objects <args>]`	In the Vivado IDE, only one device library loads for a design, so you do not need to specify the library name when you query the library cells.
`get_lib_pins`	`get_lib_pins`
`[-hsc <separator>]`
`[-regexp]` `[-nocase]` `<patterns>`	`[-regexp]` `[-nocase]` `<patterns>` `[-filter <arg>]` `[-of_objects <args>]`
`get_libs` `[-regexp]` `[-nocase]` `<patterns>`	`get_libs` `[-regexp]` `[-nocase]` `[<patterns>]` `[-filter <arg>]`
`get_nets` `[-hierarchical]` `[-hsc <separator>]` `[-regexp]` `[-nocase]` `-of_objects <objects patterns>`	`get_nets` `[-hierarchical]` `[-hsc <arg>]` `[-regexp]` `[-nocase]` `[-of_objects <args>]` `[<patterns>]` `[-filter <arg>]` `[-match_style <arg>]` `[-top_net_of_hierarchical_group]` `[-segments]` `[-boundary_type <arg>]`
`get_pins` `[-hierarchical]` `[-hsc <separator>]` `[-regexp]` `[-nocase]` `-of_objects <objects>` `<patterns>`	`get_pins` `[-hierarchical]` `[-hsc <arg>]` `[-regexp]` `[-nocase]` `[-of_objects <args>]` `[<patterns>]` `[-leaf]` `[-filter <arg>]` `[-match_style <ar>g]`
`get_ports` `[-regexp]` `[-nocase]` `<patterns>`	`get_ports` `[-regexp]` `[-nocase]` `[<patterns>]` `[-filter <arg>]` `[-of_objects <args>]` `[-match_style <arg>]`
`create_clock` `-period <period_value>` `[-name <clock_name>]` `[-waveform <edge_list>]` `[-add]` `[<source_objects>]`	`create_clock` `-period <arg>` `[-name <arg>]` `[-waveform <args>]` `[-add]` `[<objects>]`
`create_generated_clock` `[-name <clock_name>]` `-source <master_pin>` `[-edges <edge_list>]` `[-divide_by <factor>]` `[-multiply_by <factor>]` `[-duty_cycle <percent>]`	`create_generated_clock` `[-name arg>]` `[-source <args>]` `[-edges <args>]` `[-divide_by <arg>]` `[-multiply_by <arg>]` `[-duty_cycle <arg>]`
`[-invert]`
`[-edge_shift <shift_list>]` `[-add]` `[-master_clock <clock>]` `[-combinational]` `<source_objects>`	`[-edge_shift <args>]` `[-add]` `[-master_clock <arg>]` `[-combinational]` `<objects>`
`group_path` `[-name <group_name>]` `[-default]`	`group_path` `[-name <arg>]`
`[-weight <weight_value>]` `[-from <from_list>]` `[-rise_from <from_list>]` `[-fall_from <from_list>]`	`[-weight 1\|2]` `[-from <args>]`
`[-to <to_list>]` `[-rise_to <to_list>]` `[-fall_to <to_list>]`	`[-to <args>]`
`[-through <through_list>]` `[-rise_through <through_list>]` `[-fall_through <through_list>]`	`[-through <args>]`
`set_clock_groups` `[-name <name>]` `[-logically_exclusive]` `[-physically_exclusive]` `[-asynchronous]` `[-allow_paths]`	`set_clock_groups` `[-name <arg>]` `[-logically_exclusive]` `[-physically_exclusive]` `[-asynchronous]`
`-group` `<clock_list>`	`[-group <args>]`
`set_clock_latency` `[-rise]` `[-fall]` `[-min]` `[-max]` `[-source]` `[-late]` `[-early]` `[-clock <clock_list>]` `<delay>` `<object_list>`	`set_clock_latency` `[-rise]` `[-fall]` `[-min]` `[-max]` `[-source]` `[-late]` `[-early]` `[-clock <args>]` `<latency objects>`
`set_clock_sense` `[-positive]` `[-negative]` `[-pulse <pulse>]` `[-stop_propagation]` `[-clock <clock_list>]` `<pin_list>`	`set_clock_sense` `[-positive]` `[-negative]` `[-pulse <arg>]` `[-stop_propagation]` `[-clocks <args>]` `<pins>`
`set_clock_uncertainty` `[-from <from_clock>]` `[-rise_from <rise_from_clock>]` `[-fall_from <fall_from_clock>]` `[-to <to_clock>]` `[-rise_to <rise_to_clock>]` `[-fall_to <fall_to_clock>]` `[-rise]` `[-fall]`	`set_clock_uncertainty` `[-from <args>]` `[-rise_from <args>]` `[-fall_from <args>]` `[-to <args>]` `[-rise_to <args>]` `[-fall_to <args>]`
`[-setup]` `[-hold]` `<uncertainty>` `[<object_list>]`	`[-setup]` `[-hold]` `<uncertainty >` `[<objects>]`
`set_data_check` `[-from <from_object>]` `[-to <to_object>]` `[-rise_from <from_object>]` `[-fall_from <from_object>]` `[-rise_to <to_object>]` `[-fall_to <to_object>]` `[-setup]` `[-hold]` `[-clock <clock_object>]` `<value>`	`set_data_check` `[-from <args>]` `[-to <args>]` `[-rise_from <args>]` `[-fall_from <args>]` `[-rise_to <args>]` `[-fall_to <args>]` `[-setup]` `[-hold]` `[-clock <args>]` `<value>`
`set_disable_timing` `[-from <from_pin_name>]` `[-to <to_pin_name>]` `<cell_pin_list>`	`set_disable_timing` `[-from <arg>]` `[-to <arg>]` `<objects>`
`set_false_path` `[-setup]` `[-hold]` `[-rise]` `[-fall]` `[-from <from_list>]` `[-to <to_list>]` `[-through <through_list>]` `[-rise_from <rise_from_list>]` `[-rise_to <rise_to_list>]` `[-rise_through <rise_through_list>]`	`set_false_path` `[-setup]` `[-hold]` `[-rise]` `[-fall]` `[-from <args>]` `[-to <args>]` `[-through <args>]` `[-rise_from <args>]` `[-rise_to <args>]` `[-rise_through <args>]`
`[-fall_from <fall_from_list>]`	`[-fall_from <args>]`
`[-fall_to <fall_to_list>]`	`[-fall_to <args.]`
`[-fall_through <fall_through_list>]`	`[-fall_through <args>]`
	`[-reset_path]`
`set_input_delay` `[-clock <clock_name>]` `[-clock_fall]` `[-level_sensitive]`	`set_input_delay` `[-clock <args>]` `[-clock_fall]`	In the Vivado IDE, you cannot apply input delays on internal pins.
`[-rise]` `[-fall]` `[-max]` `[-min]` `[-add_delay]` `[-network_latency_included]` `[-source_latency_included]` `<delay_value>` `<port_pin_list>`	`[-rise]` `[-fall]` `[-max]` `[-min]` `[-add_delay]` `[-network_latency_included]` `[-source_latency_included]` `<delay>` `<objects>` `[-reference_pin <args>]`
`set_max_delay` `[-rise]` `[-fall]` `[-from <from_list>]` `[-to <to_list>]` `[-through <through_list>]` `[-rise_from <rise_from_list>]` `[-rise_to <rise_to_list>]` `[-rise_throughrise_through_list]`	`set_max_delay` `[-rise]` `[-fall]` `[-from <args>]` `[-to <args>]` `[-through <args>]` `[-rise_from <args>]` `[-rise_to <args>]` `[-rise_through <args>]`
`[-fall_from <fall_from_list>]` `[-fall_to <fall_to_list>]`	`[-fall_from <args>]` `[-fall_to <args>]`
`[-fall_through <fall_through_list>]`	`[-fall_through <args>]`
`<delay_value>`	`<delay>` `[-reset_path]` `[-datapath_only]`
`set_max_time_borrow` `<delay_value object_list>`	`set_max_time_borrow` `<delay objects>`
`set_min_delay` `[-rise]` `[-fall]` `[-from <from_list>]` `[-to <to_list>]` `[-through <through_list>]` `[-rise_from <rise_from_list>]` `[-rise_to <rise_to_list>]` `[-rise_through <rise_through_list>]` `[-fall_from <fall_from_list>]` `[-fall_to <fall_to_list>]` `[-fall_through <fall_through_list>]`	`set_min_delay` `[-rise]` `[-fall]` `[-from <args>]` `[-to <args>]` `[-through <args>]` `[-rise_from <args>]` `[-rise_to <args>]` `[-rise_through <args>]` `[-fall_to <args>]` `[-fall_from <args>]` `[-fall_through <args>]`
`<delay_value>`	`<delay>` `[-reset_path]`
`set_multicycle_path` `[-setup]` `[-hold]` `[-rise]` `[-fall]` `[-start]` `[-end]` `[-from <from_list>]` `[-to <to_list>]` `[-through <through_list>]` `[-rise_from <rise_from_list>]` `[-rise_to <rise_to_list>]`	`set_multicycle_path` `[-setup]` `[-hold]` `[-rise]` `[-fall]` `[-start]` `[-end]` `[-from <args>]` `[-to <args>]` `[-through <args>]` `[-rise_from <args>]` `[-rise_to <args>]`
`[-rise_through <rise_through_list>]`	`[-rise_through <args>]`
`[-fall_from <fall_from_list>]` `[-fall_to <fall_to_list>]` `[-fall_through <fall_through_list>]`	`[-fall_from <args>]` `[-fall_to <args>]` `[-fall_through <args>]`
`<path_multiplier>`	`<path_multiplier>` `[-reset_path]`
`set_output_delay` `[-clock <clock_name>]` `[-clock_fall]` `[-level_sensitive]` `[-rise]` `[-fall]` `[-max]` `[-min]` `[-add_delay]` `[-network_latency_included]` `[-source_latency_included]` `<delay_value>` `<port_pin_list>`	`set_output_delay` `[-clock <args>]` `[-clock_fall]` `[-rise]` `[-fall]` `[-max]` `[-min]` `[-add_delay]` `[-network_latency_included]` `[-source_latency_included]` `<delay>` `<objects>` `[-reference_pin <args>]`	In the Vivado IDE, you cannot apply output delays on internal pins.
`set_propagated_clock` `<object_list>`	`set_propagated_clock` `<object>`	In the Vivado IDE, all clocks are propagated by default.
`set_case_analysis` `<value port_or_pin_list>`	`set_case_analysis` `<value objects>`
`set_load` `[-min]` `[-max]` `[-subtract_pin_load]` `[-pin_load]` `[-wire_load]` `<value>` `<objects>`	`set_load` `[-max]` `[-min]` `<capacitance>` `<objects>` `[-rise]` `[-fall]`	In the Vivado IDE, the `set_load` command is relevant for power analysis only.
`set_logic_dc` `<port_list>`	`set_logic_dc` `<objects>`
`set_logic_one` `<port_list>`	`set_logic_one` `<objects>`
`set_logic_zero` `<port_list>`	`set_logic_zero` `<objects>`
`set_operating_conditions` `[-library <lib_name>]` `[-analysis_type <analysis_type>]` `[-max <max_condition>]` `[-min <min_condition>]` `[-max_library <max_lib>]` `[-min_library <min_lib>]` `[-object_list <objects>]` `[<condition>]`	`set_operating_conditions` `[-voltage <args>]` `[-grade <arg>]` `[-process <arg>]` `[-junction_temp <arg>]` `[-ambient_temp <arg>]` `[-thetaja <arg>]` `[-thetasa <arg>]` `[-airflow <arg>]` `[-heatsink <arg>]` `[-thetajb <arg>]` `[-board <arg>]` `[-board_temp <arg>]` `[-board_layers <arg>]`	In the Vivado IDE, use the `set_operating_conditions` command only to set operating conditions for power analysis. This command does not affect timing reports. The timing engine is controlled by the `config_timing_analysis` command. For more information, refer to Vivado Design Suite Tcl Command Reference Guide (UG835).

Supported SDC Commands - Supported SDC Commands - 2026.1 English - UG903

Vivado Design Suite User Guide: Using Constraints (UG903)