-quiet
and -verbose
options, the
following table does not list them.SDC 1.9 | AMD SDC | Notes |
---|---|---|
current_instance
|
current_instance
|
The Vivado
IDE handles get_ports differently when using read_xdc
-cells/-ref or the SCOPED_TO_xxx constraint file
property. |
expr
|
expr
|
|
list
|
list
|
In the Vivado IDE, a Tcl list is also used as an objects container. |
set
|
set
|
|
set_hierarchy_separator
|
set_hierarchy_separator
|
|
|
|
The set_units -time cannot change the timing unit in the Vivado IDE. |
all_clocks
|
all_clocks
|
|
all_inputs
|
all_inputs
|
|
all_outputs
|
all_outputs
|
|
all_registers
|
all_registers
|
|
|
|
|
current_design
|
current_design
|
In the Vivado IDE, the current design refers to the design loaded in memory, and cannot be changed to another module or entity than the top-level one. |
get_cells
|
|
|
|
|
The Vivado
IDE supports the -of_objects option to query the
clock object on the clock tree. |
get_lib_cells
|
get_lib_cells
|
In the Vivado IDE, because only one device library can be loaded for a design, it is not necessary to specify the library name when querying the library cells. |
|
||
|
|
|
|
||
get_lib_pins
|
get_lib_pins
|
|
|
||
|
|
|
get_libs
|
get_libs
|
|
get_nets
|
get_nets
|
|
get_pins
|
get_pins
|
|
get_ports
|
get_ports
|
|
create_clock
|
create_clock
|
|
create_generated_clock
|
create_generated_clock
|
|
|
||
|
|
|
group_path
|
group_path
|
|
|
|
|
|
|
|
|
|
|
set_clock_groups
|
set_clock_groups
|
|
|
|
|
set_clock_latency
|
set_clock_latency
|
|
set_clock_sense
|
set_clock_sense
|
|
set_clock_uncertainty
|
set_clock_uncertainty
|
|
|
|
|
set_data_check
|
set_data_check
|
|
set_disable_timing
|
set_disable_timing
|
|
set_false_path
|
set_false_path
|
|
|
|
|
|
|
|
|
|
|
|
||
set_input_delay
|
set_input_delay
|
In the Vivado IDE, input delays are not supported on internal pins. |
|
|
|
set_max_delay
|
set_max_delay
|
|
|
|
|
|
|
|
|
|
|
set_max_time_borrow
|
set_max_time_borrow
|
|
set_min_delay
|
set_min_delay
|
|
|
|
|
|
|
|
|
|
|
|
|
|
set_multicycle_path
|
set_multicycle_path
|
|
|
|
|
|
|
|
|
|
|
|
|
|
set_output_delay
|
set_output_delay
|
In the Vivado IDE, output delays are not supported on internal pins. |
|
|
|
set_propagated_clock
|
set_propagated_clock
|
In the Vivado IDE, all clocks are propagated clocks by default. |
set_case_analysis
|
set_case_analysis
|
|
set_load
|
set_load
|
In the Vivado IDE, the set_load command is relevant for power analysis only. |
|
|
|
set_logic_dc
|
set_logic_dc
|
|
set_logic_one
|
set_logic_one
|
|
set_logic_zero
|
set_logic_zero
|
|
set_operating_conditions
|
set_operating_conditions
|
In the Vivado IDE, the set_operating_conditions command: (1) sets the operating conditions for power analysis only; and (2) does not influence the timing reports. The Vivado IDE timing engine is controlled by the config_timing_analysis command. For more information on config_timing_analysis see the Vivado Design Suite Tcl Command Reference Guide (UG835). |
|